SC28L198

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10110 Xoff resume command (CRXoffre; not active in 11001 11011
Auto-Transmit Mode ). A command to cancel a previous Reserved
Host Xoff command. Upon receipt, the channel s 11011 Reset Address Recognition Status. This command clears the
transmitter will transfer a character, if any, from the interrupt status that was set when an address character
TxFIFO and begin transmission. was recognized by a disabled receiver operating in the
10111 Host Xoff command (CRXoff). This command allows tight special mode.
host CPU control of the flow control of the channel 11100 11101
transmitter. When interrupted for receipt of an Xoff Reserved
character by the receiver, the host may stop transmission 11110 Resets all UART channel registers. This command
of further characters by the channel transmitter by issuing provides a means to zero all the UART channels that are
the Host Xoff command. Any character that has been not reset to x 00 by a reset command or a hardware reset.
transferred to the TxD shift register will complete its 11111 Reserved for channels b-h, for channel a: executes a chip
transmission, including the stop bit. wide reset. Executing this command in channel a is
11000 Cancel Host transmit flow control command. Issuing this equivalent to a hardware reset with the RESETN pin.
command will cancel a previous transmit command if the Executing in channel b-h, has no effect.
Table 9. Command Register Code
Commands x 12, x13, x 14, x 15, x 1f (marked with*) are global and exist only in channel A s register space.
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Channel Command Channel Channel Command Channel
Code Code
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Command Command
CR[7:3] Description CR[7:3] Description
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00000 NOP 10000 Transmit Xon
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00001 Reserved 10001 Transmit Xoff
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00010 Reset Receiver 10010 Gang Write Xon Character Registers *
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00011 Reset Transmitter 10011 Gang Write Xoff Character Registers *
00100 ��
10100 Gang Load Xon Character Registers DC1 *
�� Reset Error Status ��
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00101 Reset Break Change Interrupt 10101 Gang Load Xoff Character Registers DC3 *
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00110 Begin Transmit Break 10110 Xoff Resume Command
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00111 End Transmit Break 10111 Host Xoff Command
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01000 Assert RTSN (I/O2 or I/O1) 11000 Cancel Transmit X Char command
�� Negate RTSN (I/O2 or I/O1) ��
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01001 ��
11001 Reserved
01010 Set time out mode on 11010 Reserved
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01011 Reserved 11011 Reset Address Recognition Status
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01100 Set time out mode off 11100 Reserved
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01101 Block Error Status configure 11101 Reserved
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01110 Reserved 11110 Reset All UART channel registers
01111 Reserved 11111 Reset Device *
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Table 10. SR Channel Status Register
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Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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Received Framing Error Parity Overrun Error�� TxRDY RxFULL RxRDY
TxEMT
Break
Error
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0 No 0 No 0 No 0 No 0 No 0 No 0 No 0 No
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1 Yes 1 Yes 1 Yes 1 Yes 1 Yes 1 Yes 1 Yes 1 Yes
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SR[7] Received Break received character. However, if a break begins in the middle of a
This bit indicates that an all zero character of the programmed character, it must last until the end of the next character in order for
length has been received without a stop bit. Only a single FIFO it to be detected.
position is occupied when a break is received; further entries to the
FIFO are inhibited until the RxD line returns to the marking state for SR[6] Framing Error (FE)
at least one half bit time (two successive edges of the internal or This bit, when set, indicates that a stop bit was not detected when
external 1x clock). When this bit is set, the change in break bit in the corresponding data character in the FIFO was received. The
the ISR (ISR[2]) is set. ISR[2] is also set when the end of the break stop bit check is made in the middle of the first stop bit position.
condition, as defined above, is detected. The break detect circuitry
is capable of detecting breaks that originate in the middle of a SR[5] Parity Error (PE)
1999 Jan 14 23
Philips Semiconductors Product specification
Octal UART for 3.3V and 5V supply voltage SC28L198
This bit is set when the with parity or force parity mode is This bit, when set, indicates that the TxFIFO is ready to be loaded
programmed and the corresponding character in the FIFO was with a character. This bit is cleared when the TxFIFO is loaded by
received with incorrect parity. In the special wake up mode , the the CPU and is set when the last character is transferred to the
parity error bit stores the received A/D bit. transmit shift register. TxRDY is reset when the transmitter is
disabled and is set when the transmitter is first enabled, e.g.,
SR[4] Overrun Error (OE)
characters loaded in the TxFIFO while the transmitter is disabled will
This bit, when set, indicates that one or more characters in the
not be transmitted. [ Pobierz całość w formacie PDF ]

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